1. Field of the Invention
The present invention relates to the use of test pad sets and vector network analyzers to de-embed test pad, routing path, and tester probe parasitics from characteristic measurements of a device under test, DUT.
2. Description of the Related Art
Generally, each new integrated circuit (IC) manufacturing process requires that components built with the new IC process be characterized (i.e. their performance tested). This requires that test components (or device under test, DUT, components), along with test pads for accessing the DUTs, be constructed for each new IC process. Characterization test equipment is then used to probe the DUTs by means of test probes applied to the DUTs' access pads. For example, to test the resistance of a resistor of a given material construction and shape, a known voltage may be applied across the resistor's test pads, and the resultant current through it observed. If the resistor's frequency response is desired, then an AC voltage may be applied at the resistor's test pads. However the test pads, signal routing path, and test probes of the characterization test equipment (or device tester) introduce additional loading effects that can alter the DUT's performance.
Therefore, the results observed by the device tester may not accurately reflect the device's true performance. Generally, these effects can be ignored at lower frequencies, but at high frequencies (i.e. above 1 GHz) the effects of the signal pads and tester probes can greatly affect a test device's performance. Under these circumstances, it is important to determine the loading effects of the tester and test pads, in order to calculate out their effect from the DUT's test results. This procedure is typically termed, “to de-embed” the test probe and test pad form the test bed.
To de-embed the loading effects of the testing equipment from a DUT, requires the determination of various electrical vectors. A device typically used to accomplish this task is a vector network analyzer, VNA. Consequently, a vector network analyzer is generally used first to determine the loading effects of the test pads and tester probes on a device. Once the loading effects are known, the device's performance can be tested and the known loading effects can be calculated out (i.e de-embedded) from the test results in order to obtain a true measure of the device's performance. Therefore in high frequency applications, the VNA calibration process needs to be performed prior to testing the performance of any new integrated circuit constructed in a new IC process.
There are several test algorithms for calibrating a VNA (i.e. obtaining the pads', routing path's, and tester probes' loading effects), but most include a short-circuit test and an open-circuit test with the pads and probes connected to a particular DUT (i.e. capacitor, resistor, diode, transistor, etc.). From the short-circuit and open-circuit results, the loading effects of the pads and probes can be determined to generate open-circuit and short-circuit electrical characterization vectors, which are then used to calculate out their loading effects. Since the layout of each DUT, and the routing path of the DUT's input/output nodes to its test pad are different, traditionally one is required to create a separate set of test pads for each type, size, and layout of a DUT, and is required to run the VNA calibration process for each set of test pads and each DUT. Since there may be many different devices of different sizes in any one circuit design, this process can be very time consuming.
For example, FIG. 1a shows a symbolic representation 7 of a test resistor 11 (i.e. DUT) and test pads 13 and 15 at both its ends, and also shows a representative layout construction 9 of resistor 11 and test pads 13 and 14. It is to be understood that the actual layout structure of resistor 11 would vary depending on the desired resistance value. But this underscores the problem since a separate test DUT would be required for each desired resistor of a given resistance value (i.e of a given size). If test probes were to be applied to pads 13 and 15, the loading effects (i.e. capacitive and resistive components) of pads 13 and 15 along with those of the test probe itself would be added to resistor 11. As a result, the observed test results would likely be inaccurate. The electrical contribution of pads 13 and 15 and of the test probes may be ignored in low frequency applications, but at high frequencies, their effects may greatly affect the frequency response of resistor 11. As explained above, the two most used electrical vector components needed to mathematically calculate out the loading affects of pads 13 and 15 and the test equipment's tester probes are an open circuit test and a short circuit test. As a result, two additional test structure are need to be constructed and measured prior to making any characterizing measurements of resistor 11.
With reference to FIG. 1b a symbolic circuit representation 17 and a layout representation 19 of the open circuit structure used to obtain the open circuit vector measurements is shown. It is to be understood that the physical distance between pads 13′ and 15′, and their physical dimensions are the same as pads 13 and 15 of FIG. 1a. The test probes of a tester, for example a VNA, would then be applied to test pads 13′ and 15′, and the open circuit test made to obtain its open-circuit, vector characteristic.
Similarly, FIG. 1c shows a short circuit test structure used to obtain the short circuit measurements needed for the short-circuit vector. Like before, a symbolic circuit representation 21 and a physical layout representation 23 are shown. Also like before, the physical layout and dimensions of pads 13″ and 15″ are the same as those of pads 13 and 15 of FIG. 1a. In the case of FIG. 1c, however, pads 13″ and 15″ are shorted together by a conductive path 25. Although coupling symbols 27 and 29 are shown, this is for the sake of completeness, and it is to be understood that if all the pads of FIGS. 1a to 1c are made of metal, and conductive path 25 is also made of metal, then no coupling via, or symbol (27 or 29) is needed. In this case, test pads 13″ and 15″ and conductive path 25 may form one continuous metal structure. The VNA's probes would then be applied to test pads 13″ and 15″, and their short circuit performance obtained.
Thus, three separate test pad structures are required to test the specific resistor 11 of FIG. 1a. If one desired to electrically characterize a different resistor, then one would need three different test pad layouts for that different resistor.
As an example, FIGS. 2a–2c show three different layout configurations needed to electrically characterize a first small capacitor 31, and FIGS. 3a–3c show three additional layout configurations needed to configure a second larger capacitor 51. In FIG. 2a, a symbolic electrical representation 33 and layout representation 30 of pads 37 and 39 coupled to capacitor 31 are shown. Prior to electrically characterizing capacitor 31, short-circuit and open-circuit performance vectors need to be taken in order to properly de-embed the loading effects of test pads 37 and 39 and the tester's probes on capacitor 31. Thus, three separate test layouts and test procedures are needed to properly obtain the electrical characteristics of capacitor 31. The first, is the open-circuit test layout shown in FIG. 2b, and the second is the short-circuit test layout shown in FIG. 2c. Both show symbolic electrical and layout configurations of their respective test pads (37′ and 39′ in FIG. 2b, and 37″ and 39″ in FIG. 2c). Like in the previous case of FIGS. 1a–1c, the dimensions and relative displacement of the test pads are the same in FIGS. 2a–2c. Also like before, coupling symbols 46–49 are shown in FIGS. 2b and 2c to maintain symmetry with coupling symbols 44 and 45 in FIG. 2a, but are not critical to the present discussion. In essence, if pads 37″ and 39″, along with coupling conductive path 50 are all metal, then they may be constructed of a single metal structure.
The point to be made is that if a second capacitor of different size, make-up, or structure needs to be characterized, then a second set of test characterizing pads and open circuit and short circuit test configurations are required, as is shown in FIGS. 3a–3c. In the case of FIG. 3a, testing a second larger capacitor 51 requires that its test pads 53 and 55 be spaced further apart than those of capacitor 31 in FIG. 2a. Therefore, another open-circuit pad layout consisting of pads 53′ and 55′ are needed, as shown in FIG. 3b, and a second set of short-circuit pads 53″ and 55″ (having shorting path 52) are needed, as shown in FIG. 3c. Furthermore, the VNA de-embedding procedure must be repeated for test pads 53′/55′ and 53″/55″ prior to properly testing capacitor 51 using test pads 53 and 55.
The structures of FIGS. 1a–1c, 2a–2c, and 3a–3c have been for passive devices. For completeness's sake, FIGS. 4a–4c show pad test configurations for an active device, i.e. a transistor 61. As shown in FIG. 4a, transistor 61 includes source electrode S, drain electrode D, and control gate electrode G. The device architecture of a transistor (and that of a capacitor and resistor) are well known in the art, and are not elaborated upon here, for conciseness. However, it is to be understood that control gate G likely consists of an implanted polysilicon layer separated from a substrate bulk (i.e. silicon substrate) by an oxide layer active acting as a gate insulator. It is further to be understood that source and drain regions S and D consist of doped regions within the substrate. It is also to be understood that if transistor 61 is a balanced device, then the source and drain electrodes may be interchanged. The layout configuration of pads 63, 65, and 67 is for illustrative purposes, and any layout configuration properly routed to the transistor's electrodes would be suitable.
In FIG. 4b, the open-circuit, symbolic electrical 62 and layout 64 representations show that the test pads 63′, 65′, and 67′ as well as their corresponding routing paths 63b, 65b, and 67b, maintain the same configuration and relative displacement as test pads 63, 65, and 67 as well as routing paths 63a, 65a, and 67a of FIG. 4a. This is also the case in the short-circuit configuration of FIG. 4c, which also show the symbolic electrical 66 and layout 68 representations. In the present case, the configuration and relative displacement as test pads 63″, 65″, and 67″ and their routing paths 63c, 65c, and 67c to where the input/output nodes of transistor 61 of FIG. 4a would mirror those of pads 63, 65, 67 and routing paths 63a, 65a, 67a of FIG. 4a. As is explained, an VNA would have to first make open-circuit measurements on the structure of FIG. 4b and short-circuit measurements on the structure of FIG. 4c, in order to obtain the needed open-circuit and short-circuit vectors to de-embed itself and the test pads 63, 65, and 67 from the testing of transistor 61.
As is evident from the above, each additional device to be tested, i.e. DUT, requires construction of at least three additional test layout configurations, one to test the DUT and two to obtain the necessary open-circuit and short-circuit electrical vector characteristics for de-embedding the DUT's test pads and the VNA's test probes. Additionally, the VNA's vector calibration sequence must be repeated for each pad-set.
With reference to FIG. 5a, another problem associated with testing a DUT is that at high frequencies, electromagnetic radiation 70 will emanate from a signal input or output pad 71. This can result in signal coupling, or capacitive coupling, to the bulk substrate 74 or to adjacent electric elements (i.e. routing paths, other pads, other DUTs, etc), not shown, which would affect the measured test results. One method of reducing the amount of electromagnetic radiation is to ground the radiation prior to it interacting with other elements. In FIG. 5b, this is done by adding a ground pad 73 to capture the electromagnetic radiation 70 radiating from one side of the signal pad 71. However, at high frequencies, this is often not enough, and it is necessary to capture both sides of the electromagnetic radiation 70 radiating from signal pad 71 by adding two ground pads 73 and 75, one at either side of signal pad 71, as is shown in FIG. 5c. 
With reference to FIG. 6, a VNA test probe will therefore actually have three contact pins 81, 83, and 85 protruding from a test probe 87. The two output pins 81 and 85 are ground pins, and the center pin 83 is a signal pin. These three pins are positioned to coincide with three test pads 82, 84, and 86 per input signal, or per output signal. The two output test pads, 82 and 86 are ground pads, which surround the center signal pad 84. This is typically known as a ground-signal-ground (or GSG) configuration. Therefore, the test pad configuration actually requires three test pads per input or output signal node of the DUT.
Consequently, the test pad configurations of FIGS. 1a–1c, 2a–2c, 3a–3c, and 4a–4c are actually not suitable for high frequency VNA applications. In addition to the input/output pads shown in theses figures, each signal pad typically requires two additional ground pads, one at either side of the signal pad. This further complicates their construction and increases the size of test pad configuration.
As explained above, the problems of de-embedding test pad and test probe components from an electrical characterization procedure for a DUT is particularly acute in high frequency (commonly referred to as RF) chip designs, which require many different test structures in order to accurately model the various components that comprise the chip. Specifically, for high-frequency (RF) designs many passive elements such as inductors and capacitors are regularly required. These elements are measured using the vector network analyzer (VNA) at frequencies of 20 GHz, or higher. At these high frequencies the ground-signal-ground (GSG) probes, described above, are required to ensure minimal stray capacitance coupling to other nearby structures. These special GSG probes require metal pads that are designed on the chip to exactly match the pitch between the ground and signal pins (i.e. the spacing from the center of pin 81 to 83, and from pin 83 to pin 85) which is typically 150 μm.
In the examples of FIGS. 1a–1c, 2a–2c, and 3a–3c, each DUT has at least two signal lines (i.e. an input node and an output node), which can be thought of as ports for determining the de-embedding electrical vectors. Therefore, at least two sets of GSG pads are needed for each passive element being tested. Depending on the size of the element, the minimum pad set size is at least 300 μm plus the pad dimension in the y-dimension and a suitable spacing in the x-direction that is large enough to fit the test element and necessary routing paths, i.e. wiring.
An example of a prior art GSG test pad configuration for a polysilicon capacitor is shown in FIG. 7. As shown, although capacitor 91 has two signal pads 93 and 95 for accessing the capacitor's two ends by means of signal routing lines 91a and 91b, four additional ground pads 92, 94, 96 and 98 are needed to use the GSG VNA tester. All four ground pads 92, 94, 96 and 98 are coupled together via routing line 99, but two ground pads are located at either end of each signal pad, 93 and 95. Specifically, ground pads 92 and 94 are placed at either side of signal pad 93, and ground pads 96 and 98 are placed at either end of signal pad 95. As it would be understood, the open-circuit and short circuit pad configurations needed for obtaining the de-embedding open-circuit and short-circuit electrical vectors would also require six pads, and have a configuration similar to that of FIG. 7, with the exception that capacitor 91 would be omitted.
In other words, every device element to be tested requires an open-circuit test and a short-circuit test pad pattern in order to obtain the electrical vectors needed to de-embed the pad, wiring and probe parasitics from the actual device under test (DUT). An example of open-circuit and short-circuit test pad configuration for capacitor 91 of FIG. 7 are shown in FIGS. 8 and 9, respectively. For the sake of brevity, all elements in FIGS. 8 and 9 similar to those of FIG. 7 have the same reference characters, and are described above. In FIG. 8, the ground routing path 99 is isolated from the routing lines 91a and 91b to establish an open-circuit, and in FIG. 9, routing lines 91a and 91b are coupled together to form a short-circuit configuration. Otherwise, the construction of FIGS. 8 and 9 mirrors that of FIG. 7.
The open-circuit and short-circuit test pad patterns must have the exact same pad configuration and wiring pattern as required for the specific DUT. Due to this limitation, every DUT requires its own set of open-circuit and short-circuit test layout with associated pad set, consumes a lot of silicon area on a given test chip.